Different configurations are required to support the two central processing unit (CPU) variants, commonly known as the dual processor (DP) and the multi-processor (MP). Additionally, current approaches use a scheme that may not work with future generation CPUs. In particular, current approaches for the bus request (BREQ) routing require a different wiring scheme for the dual processor and for the multi-processor. As a result of these different wiring schemes, two different boards are used to support the dual processor and the multi-processor. The above constraint disadvantageously requires more development efforts for particular products, increases supply chain costs, lowers product flexibility, and/or increases risks.
Therefore, the current approaches and/or technologies are limited to particular capabilities and suffer from various constraints.